mirror of
https://codeberg.org/superseriousbusiness/gotosocial.git
synced 2024-12-21 08:31:53 +03:00
66b77acb1c
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
235 lines
6.1 KiB
Go
235 lines
6.1 KiB
Go
package x86_64
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import (
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`fmt`
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)
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// ISA represents an extension to x86-64 instruction set.
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type ISA uint64
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const (
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ISA_CPUID ISA = 1 << iota
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ISA_RDTSC
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ISA_RDTSCP
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ISA_CMOV
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ISA_MOVBE
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ISA_POPCNT
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ISA_LZCNT
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ISA_TBM
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ISA_BMI
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ISA_BMI2
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ISA_ADX
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ISA_MMX
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ISA_MMX_PLUS
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ISA_FEMMS
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ISA_3DNOW
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ISA_3DNOW_PLUS
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ISA_SSE
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ISA_SSE2
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ISA_SSE3
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ISA_SSSE3
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ISA_SSE4A
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ISA_SSE4_1
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ISA_SSE4_2
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ISA_FMA3
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ISA_FMA4
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ISA_XOP
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ISA_F16C
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ISA_AVX
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ISA_AVX2
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ISA_AVX512F
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ISA_AVX512BW
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ISA_AVX512DQ
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ISA_AVX512VL
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ISA_AVX512PF
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ISA_AVX512ER
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ISA_AVX512CD
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ISA_AVX512VBMI
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ISA_AVX512IFMA
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ISA_AVX512VPOPCNTDQ
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ISA_AVX512_4VNNIW
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ISA_AVX512_4FMAPS
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ISA_PREFETCH
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ISA_PREFETCHW
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ISA_PREFETCHWT1
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ISA_CLFLUSH
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ISA_CLFLUSHOPT
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ISA_CLWB
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ISA_CLZERO
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ISA_RDRAND
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ISA_RDSEED
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ISA_PCLMULQDQ
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ISA_AES
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ISA_SHA
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ISA_MONITOR
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ISA_MONITORX
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ISA_ALL = ^ISA(0)
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)
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var _ISA_NAMES = map[ISA]string {
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ISA_CPUID : "CPUID",
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ISA_RDTSC : "RDTSC",
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ISA_RDTSCP : "RDTSCP",
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ISA_CMOV : "CMOV",
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ISA_MOVBE : "MOVBE",
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ISA_POPCNT : "POPCNT",
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ISA_LZCNT : "LZCNT",
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ISA_TBM : "TBM",
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ISA_BMI : "BMI",
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ISA_BMI2 : "BMI2",
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ISA_ADX : "ADX",
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ISA_MMX : "MMX",
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ISA_MMX_PLUS : "MMX+",
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ISA_FEMMS : "FEMMS",
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ISA_3DNOW : "3dnow!",
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ISA_3DNOW_PLUS : "3dnow!+",
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ISA_SSE : "SSE",
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ISA_SSE2 : "SSE2",
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ISA_SSE3 : "SSE3",
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ISA_SSSE3 : "SSSE3",
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ISA_SSE4A : "SSE4A",
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ISA_SSE4_1 : "SSE4.1",
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ISA_SSE4_2 : "SSE4.2",
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ISA_FMA3 : "FMA3",
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ISA_FMA4 : "FMA4",
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ISA_XOP : "XOP",
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ISA_F16C : "F16C",
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ISA_AVX : "AVX",
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ISA_AVX2 : "AVX2",
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ISA_AVX512F : "AVX512F",
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ISA_AVX512BW : "AVX512BW",
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ISA_AVX512DQ : "AVX512DQ",
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ISA_AVX512VL : "AVX512VL",
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ISA_AVX512PF : "AVX512PF",
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ISA_AVX512ER : "AVX512ER",
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ISA_AVX512CD : "AVX512CD",
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ISA_AVX512VBMI : "AVX512VBMI",
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ISA_AVX512IFMA : "AVX512IFMA",
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ISA_AVX512VPOPCNTDQ : "AVX512VPOPCNTDQ",
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ISA_AVX512_4VNNIW : "AVX512_4VNNIW",
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ISA_AVX512_4FMAPS : "AVX512_4FMAPS",
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ISA_PREFETCH : "PREFETCH",
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ISA_PREFETCHW : "PREFETCHW",
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ISA_PREFETCHWT1 : "PREFETCHWT1",
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ISA_CLFLUSH : "CLFLUSH",
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ISA_CLFLUSHOPT : "CLFLUSHOPT",
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ISA_CLWB : "CLWB",
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ISA_CLZERO : "CLZERO",
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ISA_RDRAND : "RDRAND",
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ISA_RDSEED : "RDSEED",
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ISA_PCLMULQDQ : "PCLMULQDQ",
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ISA_AES : "AES",
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ISA_SHA : "SHA",
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ISA_MONITOR : "MONITOR",
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ISA_MONITORX : "MONITORX",
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}
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var _ISA_MAPPING = map[string]ISA {
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"CPUID" : ISA_CPUID,
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"RDTSC" : ISA_RDTSC,
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"RDTSCP" : ISA_RDTSCP,
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"CMOV" : ISA_CMOV,
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"MOVBE" : ISA_MOVBE,
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"POPCNT" : ISA_POPCNT,
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"LZCNT" : ISA_LZCNT,
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"TBM" : ISA_TBM,
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"BMI" : ISA_BMI,
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"BMI2" : ISA_BMI2,
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"ADX" : ISA_ADX,
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"MMX" : ISA_MMX,
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"MMX+" : ISA_MMX_PLUS,
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"FEMMS" : ISA_FEMMS,
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"3dnow!" : ISA_3DNOW,
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"3dnow!+" : ISA_3DNOW_PLUS,
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"SSE" : ISA_SSE,
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"SSE2" : ISA_SSE2,
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"SSE3" : ISA_SSE3,
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"SSSE3" : ISA_SSSE3,
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"SSE4A" : ISA_SSE4A,
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"SSE4.1" : ISA_SSE4_1,
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"SSE4.2" : ISA_SSE4_2,
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"FMA3" : ISA_FMA3,
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"FMA4" : ISA_FMA4,
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"XOP" : ISA_XOP,
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"F16C" : ISA_F16C,
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"AVX" : ISA_AVX,
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"AVX2" : ISA_AVX2,
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"AVX512F" : ISA_AVX512F,
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"AVX512BW" : ISA_AVX512BW,
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"AVX512DQ" : ISA_AVX512DQ,
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"AVX512VL" : ISA_AVX512VL,
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"AVX512PF" : ISA_AVX512PF,
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"AVX512ER" : ISA_AVX512ER,
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"AVX512CD" : ISA_AVX512CD,
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"AVX512VBMI" : ISA_AVX512VBMI,
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"AVX512IFMA" : ISA_AVX512IFMA,
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"AVX512VPOPCNTDQ" : ISA_AVX512VPOPCNTDQ,
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"AVX512_4VNNIW" : ISA_AVX512_4VNNIW,
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"AVX512_4FMAPS" : ISA_AVX512_4FMAPS,
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"PREFETCH" : ISA_PREFETCH,
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"PREFETCHW" : ISA_PREFETCHW,
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"PREFETCHWT1" : ISA_PREFETCHWT1,
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"CLFLUSH" : ISA_CLFLUSH,
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"CLFLUSHOPT" : ISA_CLFLUSHOPT,
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"CLWB" : ISA_CLWB,
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"CLZERO" : ISA_CLZERO,
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"RDRAND" : ISA_RDRAND,
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"RDSEED" : ISA_RDSEED,
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"PCLMULQDQ" : ISA_PCLMULQDQ,
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"AES" : ISA_AES,
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"SHA" : ISA_SHA,
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"MONITOR" : ISA_MONITOR,
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"MONITORX" : ISA_MONITORX,
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}
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func (self ISA) String() string {
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if v, ok := _ISA_NAMES[self]; ok {
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return v
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} else {
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return fmt.Sprintf("(invalid: %#x)", uint64(self))
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}
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}
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// ParseISA parses name into ISA, it will panic if the name is invalid.
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func ParseISA(name string) ISA {
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if v, ok := _ISA_MAPPING[name]; ok {
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return v
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} else {
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panic("invalid ISA name: " + name)
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}
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}
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// Arch represents the x86_64 architecture.
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type Arch struct {
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isa ISA
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}
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// DefaultArch is the default architecture with all ISA enabled.
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var DefaultArch = CreateArch()
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// CreateArch creates a new Arch with all ISA enabled.
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func CreateArch() *Arch {
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return new(Arch).EnableISA(ISA_ALL)
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}
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// HasISA checks if a particular ISA was enabled.
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func (self *Arch) HasISA(isa ISA) bool {
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return (self.isa & isa) != 0
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}
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// EnableISA enables a particular ISA.
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func (self *Arch) EnableISA(isa ISA) *Arch {
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self.isa |= isa
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return self
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}
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// DisableISA disables a particular ISA.
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func (self *Arch) DisableISA(isa ISA) *Arch {
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self.isa &^= isa
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return self
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}
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// CreateProgram creates a new empty program.
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func (self *Arch) CreateProgram() *Program {
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return newProgram(self)
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}
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