mirror of
https://codeberg.org/superseriousbusiness/gotosocial.git
synced 2024-11-29 10:28:56 +03:00
675 lines
20 KiB
Go
675 lines
20 KiB
Go
package x86_64
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import (
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`encoding/binary`
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`math`
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)
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/** Operand Encoding Helpers **/
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func imml(v interface{}) byte {
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return byte(toImmAny(v) & 0x0f)
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}
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func relv(v interface{}) int64 {
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switch r := v.(type) {
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case *Label : return 0
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case RelativeOffset : return int64(r)
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default : panic("invalid relative offset")
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}
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}
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func addr(v interface{}) interface{} {
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switch a := v.(*MemoryOperand).Addr; a.Type {
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case Memory : return a.Memory
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case Offset : return a.Offset
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case Reference : return a.Reference
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default : panic("invalid memory operand type")
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}
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}
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func bcode(v interface{}) byte {
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if m, ok := v.(*MemoryOperand); !ok {
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panic("v is not a memory operand")
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} else if m.Broadcast == 0 {
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return 0
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} else {
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return 1
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}
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}
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func vcode(v interface{}) byte {
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switch r := v.(type) {
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case XMMRegister : return byte(r)
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case YMMRegister : return byte(r)
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case ZMMRegister : return byte(r)
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case MaskedRegister : return vcode(r.Reg)
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default : panic("v is not a vector register")
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}
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}
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func kcode(v interface{}) byte {
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switch r := v.(type) {
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case KRegister : return byte(r)
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case XMMRegister : return 0
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case YMMRegister : return 0
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case ZMMRegister : return 0
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case RegisterMask : return byte(r.K)
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case MaskedRegister : return byte(r.Mask.K)
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case *MemoryOperand : return toKcodeMem(r)
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default : panic("v is not a maskable operand")
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}
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}
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func zcode(v interface{}) byte {
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switch r := v.(type) {
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case KRegister : return 0
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case XMMRegister : return 0
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case YMMRegister : return 0
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case ZMMRegister : return 0
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case RegisterMask : return toZcodeRegM(r)
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case MaskedRegister : return toZcodeRegM(r.Mask)
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case *MemoryOperand : return toZcodeMem(r)
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default : panic("v is not a maskable operand")
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}
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}
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func lcode(v interface{}) byte {
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switch r := v.(type) {
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case Register8 : return byte(r & 0x07)
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case Register16 : return byte(r & 0x07)
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case Register32 : return byte(r & 0x07)
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case Register64 : return byte(r & 0x07)
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case KRegister : return byte(r & 0x07)
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case MMRegister : return byte(r & 0x07)
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case XMMRegister : return byte(r & 0x07)
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case YMMRegister : return byte(r & 0x07)
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case ZMMRegister : return byte(r & 0x07)
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case MaskedRegister : return lcode(r.Reg)
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default : panic("v is not a register")
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}
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}
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func hcode(v interface{}) byte {
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switch r := v.(type) {
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case Register8 : return byte(r >> 3) & 1
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case Register16 : return byte(r >> 3) & 1
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case Register32 : return byte(r >> 3) & 1
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case Register64 : return byte(r >> 3) & 1
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case KRegister : return byte(r >> 3) & 1
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case MMRegister : return byte(r >> 3) & 1
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case XMMRegister : return byte(r >> 3) & 1
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case YMMRegister : return byte(r >> 3) & 1
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case ZMMRegister : return byte(r >> 3) & 1
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case MaskedRegister : return hcode(r.Reg)
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default : panic("v is not a register")
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}
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}
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func ecode(v interface{}) byte {
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switch r := v.(type) {
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case Register8 : return byte(r >> 4) & 1
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case Register16 : return byte(r >> 4) & 1
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case Register32 : return byte(r >> 4) & 1
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case Register64 : return byte(r >> 4) & 1
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case KRegister : return byte(r >> 4) & 1
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case MMRegister : return byte(r >> 4) & 1
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case XMMRegister : return byte(r >> 4) & 1
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case YMMRegister : return byte(r >> 4) & 1
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case ZMMRegister : return byte(r >> 4) & 1
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case MaskedRegister : return ecode(r.Reg)
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default : panic("v is not a register")
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}
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}
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func hlcode(v interface{}) byte {
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switch r := v.(type) {
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case Register8 : return toHLcodeReg8(r)
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case Register16 : return byte(r & 0x0f)
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case Register32 : return byte(r & 0x0f)
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case Register64 : return byte(r & 0x0f)
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case KRegister : return byte(r & 0x0f)
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case MMRegister : return byte(r & 0x0f)
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case XMMRegister : return byte(r & 0x0f)
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case YMMRegister : return byte(r & 0x0f)
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case ZMMRegister : return byte(r & 0x0f)
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case MaskedRegister : return hlcode(r.Reg)
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default : panic("v is not a register")
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}
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}
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func ehcode(v interface{}) byte {
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switch r := v.(type) {
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case Register8 : return byte(r >> 3) & 0x03
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case Register16 : return byte(r >> 3) & 0x03
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case Register32 : return byte(r >> 3) & 0x03
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case Register64 : return byte(r >> 3) & 0x03
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case KRegister : return byte(r >> 3) & 0x03
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case MMRegister : return byte(r >> 3) & 0x03
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case XMMRegister : return byte(r >> 3) & 0x03
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case YMMRegister : return byte(r >> 3) & 0x03
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case ZMMRegister : return byte(r >> 3) & 0x03
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case MaskedRegister : return ehcode(r.Reg)
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default : panic("v is not a register")
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}
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}
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func toImmAny(v interface{}) int64 {
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if x, ok := asInt64(v); ok {
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return x
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} else {
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panic("value is not an integer")
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}
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}
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func toHcodeOpt(v interface{}) byte {
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if v == nil {
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return 0
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} else {
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return hcode(v)
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}
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}
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func toEcodeVMM(v interface{}, x byte) byte {
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switch r := v.(type) {
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case XMMRegister : return ecode(r)
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case YMMRegister : return ecode(r)
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case ZMMRegister : return ecode(r)
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default : return x
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}
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}
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func toKcodeMem(v *MemoryOperand) byte {
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if !v.Masked {
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return 0
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} else {
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return byte(v.Mask.K)
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}
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}
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func toZcodeMem(v *MemoryOperand) byte {
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if !v.Masked || v.Mask.Z {
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return 0
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} else {
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return 1
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}
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}
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func toZcodeRegM(v RegisterMask) byte {
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if v.Z {
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return 1
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} else {
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return 0
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}
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}
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func toHLcodeReg8(v Register8) byte {
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switch v {
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case AH: fallthrough
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case BH: fallthrough
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case CH: fallthrough
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case DH: panic("ah/bh/ch/dh registers never use 4-bit encoding")
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default: return byte(v & 0x0f)
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}
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}
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/** Instruction Encoding Helpers **/
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const (
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_N_inst = 16
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)
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const (
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_F_rel1 = 1 << iota
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_F_rel4
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)
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type _Encoding struct {
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len int
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flags int
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bytes [_N_inst]byte
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encoder func(m *_Encoding, v []interface{})
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}
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// buf ensures len + n <= len(bytes).
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func (self *_Encoding) buf(n int) []byte {
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if i := self.len; i + n > _N_inst {
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panic("instruction too long")
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} else {
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return self.bytes[i:]
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}
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}
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// emit encodes a single byte.
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func (self *_Encoding) emit(v byte) {
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self.buf(1)[0] = v
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self.len++
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}
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// imm1 encodes a single byte immediate value.
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func (self *_Encoding) imm1(v int64) {
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self.emit(byte(v))
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}
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// imm2 encodes a two-byte immediate value in little-endian.
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func (self *_Encoding) imm2(v int64) {
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binary.LittleEndian.PutUint16(self.buf(2), uint16(v))
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self.len += 2
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}
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// imm4 encodes a 4-byte immediate value in little-endian.
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func (self *_Encoding) imm4(v int64) {
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binary.LittleEndian.PutUint32(self.buf(4), uint32(v))
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self.len += 4
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}
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// imm8 encodes an 8-byte immediate value in little-endian.
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func (self *_Encoding) imm8(v int64) {
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binary.LittleEndian.PutUint64(self.buf(8), uint64(v))
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self.len += 8
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}
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// vex2 encodes a 2-byte or 3-byte VEX prefix.
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//
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// 2-byte VEX prefix:
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// Requires: VEX.W = 0, VEX.mmmmm = 0b00001 and VEX.B = VEX.X = 0
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// +----------------+
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// Byte 0: | Bits 0-7: 0xc5 |
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// +----------------+
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//
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// +-----------+----------------+----------+--------------+
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// Byte 1: | Bit 7: ~R | Bits 3-6 ~vvvv | Bit 2: L | Bits 0-1: pp |
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// +-----------+----------------+----------+--------------+
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//
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// 3-byte VEX prefix:
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// +----------------+
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// Byte 0: | Bits 0-7: 0xc4 |
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// +----------------+
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//
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// +-----------+-----------+-----------+-------------------+
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// Byte 1: | Bit 7: ~R | Bit 6: ~X | Bit 5: ~B | Bits 0-4: 0b00001 |
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// +-----------+-----------+-----------+-------------------+
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//
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// +----------+-----------------+----------+--------------+
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// Byte 2: | Bit 7: 0 | Bits 3-6: ~vvvv | Bit 2: L | Bits 0-1: pp |
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// +----------+-----------------+----------+--------------+
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//
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func (self *_Encoding) vex2(lpp byte, r byte, rm interface{}, vvvv byte) {
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var b byte
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var x byte
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/* VEX.R must be a single-bit mask */
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if r > 1 {
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panic("VEX.R must be a 1-bit mask")
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}
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/* VEX.Lpp must be a 3-bit mask */
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if lpp &^ 0b111 != 0 {
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panic("VEX.Lpp must be a 3-bit mask")
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}
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/* VEX.vvvv must be a 4-bit mask */
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if vvvv &^ 0b1111 != 0 {
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panic("VEX.vvvv must be a 4-bit mask")
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}
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/* encode the RM bits if any */
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if rm != nil {
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switch v := rm.(type) {
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case *Label : break
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case Register : b = hcode(v)
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case MemoryAddress : b, x = toHcodeOpt(v.Base), toHcodeOpt(v.Index)
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case RelativeOffset : break
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default : panic("rm is expected to be a register or a memory address")
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}
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}
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/* if VEX.B and VEX.X are zeroes, 2-byte VEX prefix can be used */
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if x == 0 && b == 0 {
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self.emit(0xc5)
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self.emit(0xf8 ^ (r << 7) ^ (vvvv << 3) ^ lpp)
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} else {
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self.emit(0xc4)
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self.emit(0xe1 ^ (r << 7) ^ (x << 6) ^ (b << 5))
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self.emit(0x78 ^ (vvvv << 3) ^ lpp)
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}
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}
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// vex3 encodes a 3-byte VEX or XOP prefix.
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//
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// 3-byte VEX/XOP prefix
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// +-----------------------------------+
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// Byte 0: | Bits 0-7: 0xc4 (VEX) / 0x8f (XOP) |
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// +-----------------------------------+
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//
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// +-----------+-----------+-----------+-----------------+
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// Byte 1: | Bit 7: ~R | Bit 6: ~X | Bit 5: ~B | Bits 0-4: mmmmm |
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// +-----------+-----------+-----------+-----------------+
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//
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// +----------+-----------------+----------+--------------+
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// Byte 2: | Bit 7: W | Bits 3-6: ~vvvv | Bit 2: L | Bits 0-1: pp |
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// +----------+-----------------+----------+--------------+
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//
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func (self *_Encoding) vex3(esc byte, mmmmm byte, wlpp byte, r byte, rm interface{}, vvvv byte) {
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var b byte
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var x byte
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/* VEX.R must be a single-bit mask */
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if r > 1 {
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panic("VEX.R must be a 1-bit mask")
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}
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/* VEX.vvvv must be a 4-bit mask */
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if vvvv &^ 0b1111 != 0 {
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panic("VEX.vvvv must be a 4-bit mask")
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}
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/* escape must be a 3-byte VEX (0xc4) or XOP (0x8f) prefix */
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if esc != 0xc4 && esc != 0x8f {
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panic("escape must be a 3-byte VEX (0xc4) or XOP (0x8f) prefix")
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}
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/* VEX.W____Lpp is expected to have no bits set except 0, 1, 2 and 7 */
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if wlpp &^ 0b10000111 != 0 {
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panic("VEX.W____Lpp is expected to have no bits set except 0, 1, 2 and 7")
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}
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/* VEX.m-mmmm is expected to be a 5-bit mask */
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if mmmmm &^ 0b11111 != 0 {
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panic("VEX.m-mmmm is expected to be a 5-bit mask")
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}
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/* encode the RM bits */
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switch v := rm.(type) {
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case *Label : break
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case MemoryAddress : b, x = toHcodeOpt(v.Base), toHcodeOpt(v.Index)
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case RelativeOffset : break
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default : panic("rm is expected to be a register or a memory address")
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}
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/* encode the 3-byte VEX or XOP prefix */
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self.emit(esc)
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self.emit(0xe0 ^ (r << 7) ^ (x << 6) ^ (b << 5) ^ mmmmm)
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self.emit(0x78 ^ (vvvv << 3) ^ wlpp)
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}
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// evex encodes a 4-byte EVEX prefix.
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func (self *_Encoding) evex(mm byte, w1pp byte, ll byte, rr byte, rm interface{}, vvvvv byte, aaa byte, zz byte, bb byte) {
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var b byte
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var x byte
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/* EVEX.b must be a single-bit mask */
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if bb > 1 {
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panic("EVEX.b must be a 1-bit mask")
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}
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/* EVEX.z must be a single-bit mask */
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if zz > 1 {
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panic("EVEX.z must be a 1-bit mask")
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}
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/* EVEX.mm must be a 2-bit mask */
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if mm &^ 0b11 != 0 {
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panic("EVEX.mm must be a 2-bit mask")
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}
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/* EVEX.L'L must be a 2-bit mask */
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if ll &^ 0b11 != 0 {
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panic("EVEX.L'L must be a 2-bit mask")
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}
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/* EVEX.R'R must be a 2-bit mask */
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if rr &^ 0b11 != 0 {
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panic("EVEX.R'R must be a 2-bit mask")
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}
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/* EVEX.aaa must be a 3-bit mask */
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if aaa &^ 0b111 != 0 {
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panic("EVEX.aaa must be a 3-bit mask")
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}
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/* EVEX.v'vvvv must be a 5-bit mask */
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if vvvvv &^ 0b11111 != 0 {
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panic("EVEX.v'vvvv must be a 5-bit mask")
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}
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/* EVEX.W____1pp is expected to have no bits set except 0, 1, 2, and 7 */
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if w1pp &^ 0b10000011 != 0b100 {
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panic("EVEX.W____1pp is expected to have no bits set except 0, 1, 2, and 7")
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}
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/* extract bits from EVEX.R'R and EVEX.v'vvvv */
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r1, r0 := rr >> 1, rr & 1
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v1, v0 := vvvvv >> 4, vvvvv & 0b1111
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/* encode the RM bits if any */
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if rm != nil {
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switch m := rm.(type) {
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case *Label : break
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case Register : b, x = hcode(m), ecode(m)
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case MemoryAddress : b, x, v1 = toHcodeOpt(m.Base), toHcodeOpt(m.Index), toEcodeVMM(m.Index, v1)
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case RelativeOffset : break
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default : panic("rm is expected to be a register or a memory address")
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}
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}
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/* EVEX prefix bytes */
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p0 := (r0 << 7) | (x << 6) | (b << 5) | (r1 << 4) | mm
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p1 := (v0 << 3) | w1pp
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p2 := (zz << 7) | (ll << 5) | (b << 4) | (v1 << 3) | aaa
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/* p0: invert RXBR' (bits 4-7)
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* p1: invert vvvv (bits 3-6)
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* p2: invert V' (bit 3) */
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self.emit(0x62)
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self.emit(p0 ^ 0xf0)
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self.emit(p1 ^ 0x78)
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self.emit(p2 ^ 0x08)
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}
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// rexm encodes a mandatory REX prefix.
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func (self *_Encoding) rexm(w byte, r byte, rm interface{}) {
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var b byte
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var x byte
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/* REX.R must be 0 or 1 */
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if r != 0 && r != 1 {
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panic("REX.R must be 0 or 1")
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}
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/* REX.W must be 0 or 1 */
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if w != 0 && w != 1 {
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panic("REX.W must be 0 or 1")
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}
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/* encode the RM bits */
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switch v := rm.(type) {
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case *Label : break
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case MemoryAddress : b, x = toHcodeOpt(v.Base), toHcodeOpt(v.Index)
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case RelativeOffset : break
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default : panic("rm is expected to be a register or a memory address")
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}
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/* encode the REX prefix */
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self.emit(0x40 | (w << 3) | (r << 2) | (x << 1) | b)
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}
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// rexo encodes an optional REX prefix.
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func (self *_Encoding) rexo(r byte, rm interface{}, force bool) {
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var b byte
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var x byte
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/* REX.R must be 0 or 1 */
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if r != 0 && r != 1 {
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panic("REX.R must be 0 or 1")
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}
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|
|
/* encode the RM bits */
|
|
switch v := rm.(type) {
|
|
case *Label : break
|
|
case Register : b = hcode(v)
|
|
case MemoryAddress : b, x = toHcodeOpt(v.Base), toHcodeOpt(v.Index)
|
|
case RelativeOffset : break
|
|
default : panic("rm is expected to be a register or a memory address")
|
|
}
|
|
|
|
/* if REX.R, REX.X, and REX.B are all zeroes, REX prefix can be omitted */
|
|
if force || r != 0 || x != 0 || b != 0 {
|
|
self.emit(0x40 | (r << 2) | (x << 1) | b)
|
|
}
|
|
}
|
|
|
|
// mrsd encodes ModR/M, SIB and Displacement.
|
|
//
|
|
// ModR/M byte
|
|
// +----------------+---------------+---------------+
|
|
// | Bits 6-7: Mode | Bits 3-5: Reg | Bits 0-2: R/M |
|
|
// +----------------+---------------+---------------+
|
|
//
|
|
// SIB byte
|
|
// +-----------------+-----------------+----------------+
|
|
// | Bits 6-7: Scale | Bits 3-5: Index | Bits 0-2: Base |
|
|
// +-----------------+-----------------+----------------+
|
|
//
|
|
func (self *_Encoding) mrsd(reg byte, rm interface{}, disp8v int32) {
|
|
var ok bool
|
|
var mm MemoryAddress
|
|
var ro RelativeOffset
|
|
|
|
/* ModRM encodes the lower 3-bit of the register */
|
|
if reg > 7 {
|
|
panic("invalid register bits")
|
|
}
|
|
|
|
/* check the displacement scale */
|
|
switch disp8v {
|
|
case 1: break
|
|
case 2: break
|
|
case 4: break
|
|
case 8: break
|
|
case 16: break
|
|
case 32: break
|
|
case 64: break
|
|
default: panic("invalid displacement size")
|
|
}
|
|
|
|
/* special case: unresolved labels, assuming a zero offset */
|
|
if _, ok = rm.(*Label); ok {
|
|
self.emit(0x05 | (reg << 3))
|
|
self.imm4(0)
|
|
return
|
|
}
|
|
|
|
/* special case: RIP-relative offset
|
|
* ModRM.Mode == 0 and ModeRM.R/M == 5 indicates (rip + disp32) addressing */
|
|
if ro, ok = rm.(RelativeOffset); ok {
|
|
self.emit(0x05 | (reg << 3))
|
|
self.imm4(int64(ro))
|
|
return
|
|
}
|
|
|
|
/* must be a generic memory address */
|
|
if mm, ok = rm.(MemoryAddress); !ok {
|
|
panic("rm must be a memory address")
|
|
}
|
|
|
|
/* absolute addressing, encoded as disp(%rbp,%rsp,1) */
|
|
if mm.Base == nil && mm.Index == nil {
|
|
self.emit(0x04 | (reg << 3))
|
|
self.emit(0x25)
|
|
self.imm4(int64(mm.Displacement))
|
|
return
|
|
}
|
|
|
|
/* no SIB byte */
|
|
if mm.Index == nil && lcode(mm.Base) != 0b100 {
|
|
cc := lcode(mm.Base)
|
|
dv := mm.Displacement
|
|
|
|
/* ModRM.Mode == 0 (no displacement) */
|
|
if dv == 0 && mm.Base != RBP && mm.Base != R13 {
|
|
if cc == 0b101 {
|
|
panic("rbp/r13 is not encodable as a base register (interpreted as disp32 address)")
|
|
} else {
|
|
self.emit((reg << 3) | cc)
|
|
return
|
|
}
|
|
}
|
|
|
|
/* ModRM.Mode == 1 (8-bit displacement) */
|
|
if dq := dv / disp8v; dq >= math.MinInt8 && dq <= math.MaxInt8 && dv % disp8v == 0 {
|
|
self.emit(0x40 | (reg << 3) | cc)
|
|
self.imm1(int64(dq))
|
|
return
|
|
}
|
|
|
|
/* ModRM.Mode == 2 (32-bit displacement) */
|
|
self.emit(0x80 | (reg << 3) | cc)
|
|
self.imm4(int64(mm.Displacement))
|
|
return
|
|
}
|
|
|
|
/* all encodings below use ModRM.R/M = 4 (0b100) to indicate the presence of SIB */
|
|
if mm.Index == RSP {
|
|
panic("rsp is not encodable as an index register (interpreted as no index)")
|
|
}
|
|
|
|
/* index = 4 (0b100) denotes no-index encoding */
|
|
var scale byte
|
|
var index byte = 0x04
|
|
|
|
/* encode the scale byte */
|
|
if mm.Scale != 0 {
|
|
switch mm.Scale {
|
|
case 1 : scale = 0
|
|
case 2 : scale = 1
|
|
case 4 : scale = 2
|
|
case 8 : scale = 3
|
|
default : panic("invalid scale value")
|
|
}
|
|
}
|
|
|
|
/* encode the index byte */
|
|
if mm.Index != nil {
|
|
index = lcode(mm.Index)
|
|
}
|
|
|
|
/* SIB.Base = 5 (0b101) and ModRM.Mode = 0 indicates no-base encoding with disp32 */
|
|
if mm.Base == nil {
|
|
self.emit((reg << 3) | 0b100)
|
|
self.emit((scale << 6) | (index << 3) | 0b101)
|
|
self.imm4(int64(mm.Displacement))
|
|
return
|
|
}
|
|
|
|
/* base L-code & displacement value */
|
|
cc := lcode(mm.Base)
|
|
dv := mm.Displacement
|
|
|
|
/* ModRM.Mode == 0 (no displacement) */
|
|
if dv == 0 && cc != 0b101 {
|
|
self.emit((reg << 3) | 0b100)
|
|
self.emit((scale << 6) | (index << 3) | cc)
|
|
return
|
|
}
|
|
|
|
/* ModRM.Mode == 1 (8-bit displacement) */
|
|
if dq := dv / disp8v; dq >= math.MinInt8 && dq <= math.MaxInt8 && dv % disp8v == 0 {
|
|
self.emit(0x44 | (reg << 3))
|
|
self.emit((scale << 6) | (index << 3) | cc)
|
|
self.imm1(int64(dq))
|
|
return
|
|
}
|
|
|
|
/* ModRM.Mode == 2 (32-bit displacement) */
|
|
self.emit(0x84 | (reg << 3))
|
|
self.emit((scale << 6) | (index << 3) | cc)
|
|
self.imm4(int64(mm.Displacement))
|
|
}
|
|
|
|
// encode invokes the encoder to encode this instruction.
|
|
func (self *_Encoding) encode(v []interface{}) int {
|
|
self.len = 0
|
|
self.encoder(self, v)
|
|
return self.len
|
|
}
|