mirror of
https://codeberg.org/superseriousbusiness/gotosocial.git
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482 lines
7.5 KiB
Go
482 lines
7.5 KiB
Go
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// cmd/9c/9.out.h from Vita Nuova.
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package mips
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import (
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"github.com/twitchyliquid64/golang-asm/obj"
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)
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
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/*
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* mips 64
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*/
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const (
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NSNAME = 8
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NSYM = 50
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NREG = 32 /* number of general registers */
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NFREG = 32 /* number of floating point registers */
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NWREG = 32 /* number of MSA registers */
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)
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const (
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REG_R0 = obj.RBaseMIPS + iota // must be a multiple of 32
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REG_R1
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REG_R2
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REG_R3
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REG_R4
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REG_R5
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REG_R6
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REG_R7
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_R16
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REG_R17
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REG_R18
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REG_R19
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REG_R20
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REG_R21
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REG_R22
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REG_R23
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REG_R24
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REG_R25
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REG_R26
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REG_R27
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REG_R28
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REG_R29
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REG_R30
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REG_R31
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REG_F0 // must be a multiple of 32
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// co-processor 0 control registers
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REG_M0 // must be a multiple of 32
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REG_M1
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REG_M2
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REG_M3
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REG_M4
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REG_M5
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REG_M6
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REG_M7
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REG_M8
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REG_M9
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REG_M10
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REG_M11
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REG_M12
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REG_M13
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REG_M14
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REG_M15
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REG_M16
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REG_M17
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REG_M18
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REG_M19
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REG_M20
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REG_M21
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REG_M22
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REG_M23
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REG_M24
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REG_M25
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REG_M26
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REG_M27
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REG_M28
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REG_M29
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REG_M30
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REG_M31
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// FPU control registers
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REG_FCR0 // must be a multiple of 32
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REG_FCR1
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REG_FCR2
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REG_FCR3
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REG_FCR4
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REG_FCR5
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REG_FCR6
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REG_FCR7
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REG_FCR8
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REG_FCR9
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REG_FCR10
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REG_FCR11
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REG_FCR12
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REG_FCR13
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REG_FCR14
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REG_FCR15
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REG_FCR16
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REG_FCR17
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REG_FCR18
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REG_FCR19
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REG_FCR20
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REG_FCR21
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REG_FCR22
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REG_FCR23
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REG_FCR24
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REG_FCR25
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REG_FCR26
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REG_FCR27
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REG_FCR28
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REG_FCR29
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REG_FCR30
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REG_FCR31
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// MSA registers
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// The lower bits of W registers are alias to F registers
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REG_W0 // must be a multiple of 32
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REG_W1
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REG_W2
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REG_W3
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REG_W4
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REG_W5
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REG_W6
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REG_W7
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REG_W8
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REG_W9
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REG_W10
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REG_W11
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REG_W12
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REG_W13
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REG_W14
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REG_W15
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REG_W16
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REG_W17
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REG_W18
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REG_W19
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REG_W20
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REG_W21
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REG_W22
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REG_W23
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REG_W24
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REG_W25
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REG_W26
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REG_W27
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REG_W28
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REG_W29
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REG_W30
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REG_W31
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REG_HI
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REG_LO
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REG_LAST = REG_LO // the last defined register
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REG_SPECIAL = REG_M0
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REGZERO = REG_R0 /* set to zero */
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REGSP = REG_R29
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REGSB = REG_R28
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REGLINK = REG_R31
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REGRET = REG_R1
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REGARG = -1 /* -1 disables passing the first argument in register */
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REGRT1 = REG_R1 /* reserved for runtime, duffzero and duffcopy */
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REGRT2 = REG_R2 /* reserved for runtime, duffcopy */
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REGCTXT = REG_R22 /* context for closures */
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REGG = REG_R30 /* G */
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REGTMP = REG_R23 /* used by the linker */
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FREGRET = REG_F0
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)
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// https://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td search for DwarfRegNum
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// https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/mips/mips.c?view=co&revision=258099&content-type=text%2Fplain search for mips_dwarf_regno
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// For now, this is adequate for both 32 and 64 bit.
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var MIPSDWARFRegisters = map[int16]int16{}
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func init() {
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// f assigns dwarfregisters[from:to] = (base):(to-from+base)
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f := func(from, to, base int16) {
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for r := int16(from); r <= to; r++ {
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MIPSDWARFRegisters[r] = (r - from) + base
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}
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}
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f(REG_R0, REG_R31, 0)
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f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers -- see cmd/compile/internal/ssa/gen/MIPSOps.go
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MIPSDWARFRegisters[REG_HI] = 64
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MIPSDWARFRegisters[REG_LO] = 65
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// The lower bits of W registers are alias to F registers
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f(REG_W0, REG_W31, 32)
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}
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const (
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BIG = 32766
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)
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const (
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/* mark flags */
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FOLL = 1 << 0
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LABEL = 1 << 1
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LEAF = 1 << 2
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SYNC = 1 << 3
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BRANCH = 1 << 4
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LOAD = 1 << 5
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FCMP = 1 << 6
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NOSCHED = 1 << 7
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NSCHED = 20
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)
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const (
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C_NONE = iota
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C_REG
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C_FREG
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C_FCREG
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C_MREG /* special processor register */
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C_WREG /* MSA registers */
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C_HI
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C_LO
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C_ZCON
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C_SCON /* 16 bit signed */
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C_UCON /* 32 bit signed, low 16 bits 0 */
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C_ADD0CON
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C_AND0CON
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C_ADDCON /* -0x8000 <= v < 0 */
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C_ANDCON /* 0 < v <= 0xFFFF */
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C_LCON /* other 32 */
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C_DCON /* other 64 (could subdivide further) */
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C_SACON /* $n(REG) where n <= int16 */
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C_SECON
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C_LACON /* $n(REG) where int16 < n <= int32 */
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C_LECON
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C_DACON /* $n(REG) where int32 < n */
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C_STCON /* $tlsvar */
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C_SBRA
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C_LBRA
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C_SAUTO
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C_LAUTO
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C_SEXT
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C_LEXT
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C_ZOREG
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C_SOREG
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C_LOREG
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C_GOK
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C_ADDR
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C_TLS
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C_TEXTSIZE
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C_NCLASS /* must be the last */
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)
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const (
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AABSD = obj.ABaseMIPS + obj.A_ARCHSPECIFIC + iota
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AABSF
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AABSW
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AADD
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AADDD
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AADDF
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AADDU
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AADDW
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AAND
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ABEQ
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ABFPF
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ABFPT
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ABGEZ
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ABGEZAL
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ABGTZ
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ABLEZ
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ABLTZ
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ABLTZAL
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ABNE
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ABREAK
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ACLO
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ACLZ
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ACMOVF
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ACMOVN
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ACMOVT
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ACMOVZ
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ACMPEQD
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ACMPEQF
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ACMPGED
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ACMPGEF
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ACMPGTD
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ACMPGTF
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ADIV
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ADIVD
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ADIVF
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ADIVU
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ADIVW
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AGOK
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ALL
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ALLV
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ALUI
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AMADD
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AMOVB
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AMOVBU
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AMOVD
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AMOVDF
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AMOVDW
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AMOVF
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AMOVFD
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AMOVFW
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AMOVH
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AMOVHU
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AMOVW
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AMOVWD
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AMOVWF
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AMOVWL
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AMOVWR
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AMSUB
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AMUL
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AMULD
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AMULF
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AMULU
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AMULW
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ANEGD
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ANEGF
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ANEGW
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ANEGV
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ANOOP // hardware nop
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ANOR
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AOR
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AREM
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AREMU
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ARFE
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ASC
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ASCV
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ASGT
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ASGTU
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ASLL
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ASQRTD
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ASQRTF
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ASRA
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ASRL
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ASUB
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ASUBD
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ASUBF
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ASUBU
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ASUBW
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ASYNC
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ASYSCALL
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ATEQ
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ATLBP
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ATLBR
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ATLBWI
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ATLBWR
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ATNE
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AWORD
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AXOR
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||
|
|
|
||
|
|
/* 64-bit */
|
||
|
|
AMOVV
|
||
|
|
AMOVVL
|
||
|
|
AMOVVR
|
||
|
|
ASLLV
|
||
|
|
ASRAV
|
||
|
|
ASRLV
|
||
|
|
ADIVV
|
||
|
|
ADIVVU
|
||
|
|
AREMV
|
||
|
|
AREMVU
|
||
|
|
AMULV
|
||
|
|
AMULVU
|
||
|
|
AADDV
|
||
|
|
AADDVU
|
||
|
|
ASUBV
|
||
|
|
ASUBVU
|
||
|
|
|
||
|
|
/* 64-bit FP */
|
||
|
|
ATRUNCFV
|
||
|
|
ATRUNCDV
|
||
|
|
ATRUNCFW
|
||
|
|
ATRUNCDW
|
||
|
|
AMOVWU
|
||
|
|
AMOVFV
|
||
|
|
AMOVDV
|
||
|
|
AMOVVF
|
||
|
|
AMOVVD
|
||
|
|
|
||
|
|
/* MSA */
|
||
|
|
AVMOVB
|
||
|
|
AVMOVH
|
||
|
|
AVMOVW
|
||
|
|
AVMOVD
|
||
|
|
|
||
|
|
ALAST
|
||
|
|
|
||
|
|
// aliases
|
||
|
|
AJMP = obj.AJMP
|
||
|
|
AJAL = obj.ACALL
|
||
|
|
ARET = obj.ARET
|
||
|
|
)
|
||
|
|
|
||
|
|
func init() {
|
||
|
|
// The asm encoder generally assumes that the lowest 5 bits of the
|
||
|
|
// REG_XX constants match the machine instruction encoding, i.e.
|
||
|
|
// the lowest 5 bits is the register number.
|
||
|
|
// Check this here.
|
||
|
|
if REG_R0%32 != 0 {
|
||
|
|
panic("REG_R0 is not a multiple of 32")
|
||
|
|
}
|
||
|
|
if REG_F0%32 != 0 {
|
||
|
|
panic("REG_F0 is not a multiple of 32")
|
||
|
|
}
|
||
|
|
if REG_M0%32 != 0 {
|
||
|
|
panic("REG_M0 is not a multiple of 32")
|
||
|
|
}
|
||
|
|
if REG_FCR0%32 != 0 {
|
||
|
|
panic("REG_FCR0 is not a multiple of 32")
|
||
|
|
}
|
||
|
|
if REG_W0%32 != 0 {
|
||
|
|
panic("REG_W0 is not a multiple of 32")
|
||
|
|
}
|
||
|
|
}
|